1. Field of the Invention
The invention relates to a method for fabricating a mask ROM, and more particularly, to a method for fabricating a buried bit line of a mask ROM.
2. Description of the Prior Art
A read-only memory (ROM) is a nonvolatile memory where information is permanently stored through the use of custom masks during fabrication. Mask ROMs with buried bit lines (flat cell) are the most popular types of ROM. Conventionally, the buried bit lines are formed by doping impurities into the substrate through a bit line mask. A high-dosage ion implantation process is used to reduce the buried bit line sheet resistance. When the integration increases, i.e. a smaller device size, the buried bit line width, namely the channel critical dimension (CD) also shrinks. Therefore, when the wafer is subjected to high temperature conditions in subsequent processing steps, the doping impurities within the buried bit lines will diffuse outwardly and towards one another causing punch-through to take place between adjacent buried bit lines.
In order to prevent the punch-through phenomenon between adjacent buried bit lines, a conventional cell punch-through (CPT) ion implantation process through a CPT mask is performed to isolate the adjacent buried bit lines and to prevent the diffusion of impurities from the buried bit lines. FIG. 1 to FIG. 2 are schematic diagrams of a conventional method for fabricating buried bit lines 20 of a mask ROM. Referring to FIG. 1, a semiconductor substrate 10 comprising a P-type well 12 is provided. Firstly, the surface of the semiconductor substrate 10 is thermally oxidized to form a pad oxide layer 14 with a thickness between 125 and 250 angstroms (Å). A photoresist layer (not shown) is coated on the pad oxide layer 14 and patterned as is conventional in the art to form a photoresist mask 16 having openings where buried bit lines 20 are to be formed within the semiconductor substrate 10. An ion implantation process 18 is performed through the photoresist mask 16. Typically, arsenic (As) ions are implanted at a dosage of between 1.5×1015 and 3×1015 atoms/cm2 and at an energy level between 40 and 80 KeV to form the buried bit lines 20 within areas of the P-type well 12 which are not shielded by the photoresist mask 16.
Referring to FIG. 2, a CPT halo implantation process 22 is performed through the photoresist mask 16 to form halo regions 24 within the P-type well 12 encompassing the buried bit lines 20. A typical CPT halo ion implantation process 22 implants boron (B) ions at a dosage between 1.2×1013 and 1.5×1013 atoms/cm2 and at an energy level between 100 and 140 KeV. This results in longer lateral diffusion areas 24, which encompass the buried bit lines 20. The lateral diffusion areas 24 are used to isolate the adjacent buried bit lines 20.
The conventional CRT halo ion implantation process 22 is utilized to form the halo regions 24, encompassing the buried bit lines 20 for reducing punch-through phenomenon between the adjacent buried bit lines 20. However, when the mask ROM dimension shrinks, the width of each buried bit line also shrinks and the sheet resistance of the buried bit line increases. In addition, the punch-through voltage between the adjacent buried bit lines becomes unacceptably low. Therefore, the high-dosage and the CPT halo ion implantation process 22 are not suitable for preventing punch-through phenomenon between the adjacent buried bit lines 20.
Another method for forming a lightly doped drain (LDD) by utilizing a polysilicon spacer as a mask is used to fabricate the word lines. Since the polysilicon spacer is difficult to remove, this method is unsuitable for the fabrication of the buried bit lines. As the integration of the IC and the shrinkage of the channel critical dimension continue, a method for fabricating a buried bit line of a mask ROM that can reduce the hot carrier effect is desired.